(1) Field of the Invention
This invention relates to a shift register, and more particularly to a shift register with a latch circuit suitable for a serial arithmetic logic unit.
(2) Description of the Prior Art
A serial arithmetic logic unit (serial ALU) consists of a shift register which has a required number of bits, and a 1-bit ALU which is connected to the least significant bit of the shift register and which executes an operation corresponding to one bit in one cycle and feeds the result back to the most significant bit of the shift register. By way of example, it is applied as a peripheral equipment in order to determine the "on" and "off" timings of control signals, etc. in various control systems employing data processors.
The serial ALU for such uses requires a shift register with a latch circuit in order to set desired value data into the shift register and to read out operated result data from the shift register. In the case where the serial ALU and circuits associated therewith are put into the form of a LSI so as to fabricate a device which is multipurpose for various control systems, the shift register with the latch circuit needs to be made as a circuit arrangement exhibiting a low power dissipation and suited to the form of a LSI.